Microsemi presenters will explain why Microsemi FPGAs are lower power, showcase competitive data and provide a demonstration of how to analyze power for your own design. SmartFusion®2 SoC FPGAs and IGLOO®2 FPGAs are mainstream FPGAs equipped with 5G SERDES, DDR3 Controllers, PCI Express hard cores and a sophisticated microprocessor sub-system. However, unlike SRAM based FPGAs, the underlying LUT FPGA fabric is designed using flash. The non-volatile flash-based technology used in this cost optimized architecture provides up to 10X less static power than competing FPGAs. This, coupled with other power saving features including extensive hard IP, a power-optimized embedded microprocessor subsystem and industry leading low-power transceiver technology, makes these FPGAs up to 30-50% lower total power than competing FPGAs.

In this webinar, you will learn about

  • Architectural features that result in the lowest power consumption FPGAs in the industry in terms of inrush current, static power and total power
  • Power estimators and analyzers, and power measurement on evaluation kits
  • How these devices compare with competitive SERDES-based cost-optimized features

The webinar will also include a demonstration taking an example design through the entire design flow, from design entry, through synthesis and layout to power analysis and measurement of power on the actual device.