Memory Optimization Techniques for High-Speed Video SoCs
DTV manufacturers continue to push for improved picture quality and higher resolution — all with additional features at lower price points. These requirements are driving further integration along with increased bandwidth requirements for DTV SoCs (System-on-a-Chip). This increased SoC complexity necessitates the ability to look at data flows through the system and their impact on memory efficiency. Graphics processors, display processors and H.264 cores, along with additional cores, are all competing for memory resources.
In this webinar, Sonics examines the system bandwidth requirements of each of the critical processing blocks in a video SoC in order to optimize the data flow to the memory sub-systems. The presenter will also look at ways to partition the system to insure effective utilization of memory, along with effective memory scheduling.
Who should attend:
Developers, SoC design engineers, engineering managers, system architects responsible for and/or designing digital video applications.
|Ravi Chopra is an applications engineer at Silicon Valley-based Sonics, Inc. He is responsible for both pre- and post-sales technical support activities within North America, and has a broad range of expertise in high-end DSP applications. Additionally, Chopra is a specialist in modeling SoC performance at the ESL level and is currently working with a number of leading semiconductor customers in this capacity.
Prior to Sonics, he spent several years at Forte Design Systems serving as an expert in modeling customer designs for high-level ESL synthesis. Earlier in his career, Chopra worked at Cadence Design Systems as a digital verification engineer.
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