Meeting 90-nm to 10-nm Physical IP Design Requirements for Wearables and Application Processors
The demand for physical IP in 90-nm to 10-nm process nodes is driven by the market requirements for wearable devices/IoT
and application processors that require increased integration for next-generation mobile devices.
The technical requirements, process technologies and IP design approaches for each application are unique. The rise in wearable/IoT
applications has given a new impetus to the established nodes (90-nm and 55-nm bulk CMOS), while leading-edge nodes (14/16-nm
and 10-nm FinFET) are required to support high-performance, low-power application processors in mobile devices. Both markets
require IP tailored for the specific application and supported by the IP ecosystem.
This technical webinar will review the process and IP requirements for wearable/IoT devices and mobile application processors.
It will describe the different design approaches for physical IP from 90-nm to 10-nm for these markets. Finally, the webinar
will review the importance of close collaboration between the IP provider and foundries to help ensure successful IP implementation
What You Will Learn:
- Technical requirements for wearable devices and application processors
- Differentiating design approaches for physical IP from 90-nm to 10-nm for specific markets
- How the close collaboration between the IP provider and foundries helps ensure successful IP implementation and ramp-up
Who Should Attend:
SoC designers, architects, and managers interested in designing and implementing IP for IoT/wearable applications or mobile
Sr. Director of Marketing for the DesignWare Analog/Mixed Signal IP
Navraj Nandra is the Sr. Director of Marketing for the DesignWare Analog/Mixed Signal IP, Embedded Memories and Logic Libraries at Synopsys. He has worked in the semiconductor industry since the mid 80’s as an analog/mixed signal IC designer for Philips Semiconductors, Austria Micro Systems, (San Jose & Austria) and EM-Marin (Switzerland). He has been responsible for the complete design of a number of analog front ends in application areas such as digital audio, RFID and automotive. He joined Synopsys from Barcelona Design where he was Director of Application Engineering. During his four years at Barcelona he was responsible for pre- and post-sales support for Barcelona’s analog synthesis technology.
Navraj holds a master’s degree in Microelectronics, majoring in analog IC design, from Brunel University and a post-graduate diploma in Process Technology from Middlesex University. He has presented at numerous technical conferences on mixed-signal design, analog IP and analog synthesis/EDA.
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