This webinar, developed by Cadence R&D, will demonstrate the technical aspects of the UVM Reference Flow so that users can immediately employ this new environment to improve their verification productivity. The Universal Verification Methodology (UVM) Reference Flow gives the UVM community a standardized set of design and verification components with which to test and validate their flows. Combined with the recent book, “A Practical Guide to Adopting the Universal Verification Methodology”, users now have a complete text-based and executable reference flow to guide their UVM developments.

Registrants will learn:

  • the design and verification components of UVM
  • the theory and practical aspects behind the methodology
  • how to apply the methodology using reference flow examples
  • the legal responsibilities of users who decide to incorporate the UVM Reference Flow as part of their process.

Estimated length:
60 mins

Who should attend:

  • Verification engineers and management
  • Design engineers and management


Swami Venkatesan, Solutions Engineer
Swaminathan Venkatesan has over 10 years of experience in Design and Verification of complex network asic’s, processors and SoC. He is currently working at Cadence Design Systems, Bangalore as the Technical lead for Incisive Verification Kit. His interests include SoC Verification Methdologies, System Low Power verification and Metric driven Acceleration. Swami has presented verification seminars and workshop at various conferences organized by IPSoC, VLSI Society of India, Dvclub and at CDNLive!. Prior to joining Cadence, he has worked with Intel as a micro-processor design engineer and with Wipro technologies as Sr. VLSI design engineer. Swami holds a Masters Degree from Indian Institute of Science and a Bachelors from Madras University.

Nick Heaton, Solutions Architect

Nick is an ASIC and EDA veteran with more than 25 years experience in design and verification of complex SoCs. Nick graduated from Brunel University, London in 1983 with First Class Honours in Engineering and Management Systems initially working as an ASIC designer for ICL after which he founded specialist ASIC Design and Verification Company Excel Consultants in 1993 servicing customers such as ARM and Altera. In 2002 Nick joined Verisity as Manager of Northern European Consulting Engineering. Nick currently works in Cadence RnD as a Senior Solution Architect with special responsibility for the Verification Kit, a complex and realistic golden example of verification methodologies and technologies across all of Cadences front-end products.
John Brennan, Product Management
John has held a product management role at Cadence for ten years. He is responsible for Incisive Enterprise Manager, the Incisive Verification Kit and the UVM Reference Flow.