M-PCIe: Utilizing Low-Power PCI Express in Mobile Designs
Designers utilizing PCI Express are looking to lower the power of their designs by incorporating the M-PCIe ECN from PCI-SIG. The recently released M-PCIe ECN adapts the PCI Express protocol for use with the MIPI M-PHY, benefiting applications that require low-power usage such as mobile products. To incorporate PCI Express with the M-PHY, device designers should understand the top issues they’ll need to consider.
This advanced technical webinar will begin with a quick overview of the specification and its application space, and then go into details such as bandwidth and clocking considerations, PHY interface differences, power management impacts, and the tradeoffs related to choices around link-layer changes. These changes may impact the transaction and application layers of devices moving from PCIe to M-PCIe, and the webinar will detail those issues. A basic understanding of PCI Express concepts is helpful.
Attendees will learn:
- M-PCIe bandwidth and clocking considerations
- M-PCIe power management
- The tradeoffs related to the link-layer changes
- PHY interface, transaction layer, and application layer differences between PCIe and M-PCIe
Who should attend:
- System architects
- PCI Express device designers
- Mobile device designers
Scott Knowlton, Product Marketing Manager, Sr. Staff, DesignWare PCI Express, PCI-X, PCI and SATA IP, Synopsys
Scott Knowlton joined Synopsys in 1997 and has extensive experience in PCI Express, SATA, and AMBA IP as well as Synopsys’ coreTools product lines. Prior to joining Synopsys, Scott worked in simulation, synthesis and mixed signal solutions at Cadence Design Systems after several engineering and project management positions in ASIC development at Encore Computer, Intrinsix, and Raytheon. Scott earned his Bachelor of Science degree in Electrical Engineering from the University of Michigan.
Richard Solomon, Technical Marketing Manager, DesignWare PCI Express Controller IP, Synopsys
Richard Solomon has been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec. Prior to joining Synopsys, Richard architected and led the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. He has served on the PCI-SIG Board of Directors for over 10 years, and is currently Vice-President of the PCI-SIG. Richard holds a BSEE from Rice University and 25 US Patents, many of which relate to PCI technology.
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