Low Power Solutions for Your Virtex-6 and Spartan-6 FPGA Designs
As an alternative to ASICs and ASSPs, FPGAs enable manufacturers of digital electronic systems to accelerate new products to market and increase product differentiation while reducing cost and risk. Engineers are increasing their focus on power consumption as a consideration for component selection and techniques for power management are becoming more important to successful system design. Companies forced to cut resources need to reduce power with less effort.
Xilinx has adopted a holistic approach to ensure system designers can achieve power-optimized designs with Virtex®-6 and Spartan®-6 FPGAs. New software based power optimization is introduced in IDS 12 and In this webcast we examine the factors that contribute to FPGA power consumption and review the measures Xilinx has taken regarding process and device architecture to control power. We also present tools, and software options that enable engineers to easily create FPGA-based designs that achieve demanding performance goals with strict power budgets.
Attendees will learn to:
- Identify factors that can influence power in an FPGA design
- Utilize the Spartan-6 and Virtex-6 FPGA features, tools, and device options to reduce overall power consumption
- Use the Xilinx Power Analyzer to identify power issues
- Leverage new power optimization in the ISE Design Suite 12 to dramatically reduce dynamic power
Who Should Attend:
- Hardware system designers
- System architects
- Project managers
- PCB designers
- Anyone interested in lowering power in their FPGA designs
Jameel Hussein Technical Marketing Manager – Worldwide Marketing and Business Development
Jameel has worked at Xilinx for over 5 years and has been primarily focused in the area of power consumption for Xilinx’s current and future products. Jameel has a Computer Engineering degree from California Polytechnic University in San Luis Obispo and is a US patent holder.
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