Innovations in Resolution Enhancement Techniques (RETs) have allowed the manufacture of designs near the theoretical limits of lithographic processing capabilities. Operating at the limits of wafer imaging capabilities increases the risk of process-induced hotspot failures, resulting in delays in bringing a design to market. Proteus LRC is Synopsys’ next-generation lithography rule check tool and has been designed to minimize these risks and improve first-pass yield. Comprehensive standard checks have been developed for fast deployment on today’s existing technology and leading edge features have been incorporated to support DPT and EUV processes. Learn about this new product and how it can be used to accelerate your technology ramp. 

Who should attend:
Engineers and managers in the areas of photolithography, OPC/RET and mask tapeout.

Kunal Taravade 

Sr. Applications Engineering Manager, Synopsys

Kunal Taravade has over 15 years of experience in lithography and OPC/RET. He is currently Senior Applications Engineering Manager in the Silicon Engineering Group at Synopsys. Part of his responsibility is for the product development of Proteus LRC. Prior to this he was a Staff Engineer at LSI Logic (formerly Symbios, Inc.) for 11 years where he held positions in Lithography Manufacturing, Lithography Development, and OPC/RET development. 

Travis Brist 

Sr. Product Marketing Manager, Synopsys

Travis Brist has over 16 years of combined experience in photolithography and RET. He is a Senior Product Marketing Manager at Synopsys in the Manufacturing Products Group supporting the Proteus products. Prior to this he was a Senior Technical Marketing Engineer at Mentor Graphics where he managed and defined new product development and worked on strategic customer engagements. He has also held various photolithography engineering positions at LSI Logic and Cypress Semiconductor in the areas of process engineering, process development, and the application of OPC. 

Tim Tsuei

Corporate Applications Engineering Manager