Ever wonder whether the challenges of using partial reconfiguration are worth the benefits? Now, there’s an easy-to-use, fine-grain partial reconfiguration methodology that delivers lower cost and power and higher system uptime. What’s more, you don’t need to understand the intricacies of FPGA architecture to get more usable density from your device.
View this 15-minute webcast to learn how:

  • Our partial reconfiguration flow works
  • Our flow provides cost, power, and design productivity advantages
  • Our new 28-nm Stratix® V FPGAs support partial reconfiguration
  • You can use the flow to develop more cost-effective designs for applications like optical transport network (OTN) multiplexing transponders and software-defined radio

Ajay Jagtiani, Software Technical Marketing Manager 

Ajay Jagtiani joined Altera in 2005 and is currently a member of the software marketing team, serving as a software technical marketing manager. In this role, Mr. Jagtiani is responsible for planning timing closure and functional verification features in Altera’s Quartus II development software. He also provides support to third-party vendors working with Altera. Jagtiani has over 13 years of experience in the semiconductor industry, working at a variety of companies including Atrenta, Synplicity and Lattice Semiconductor. He holds an MBA in financial analysis from the University of San Francisco, an MSEE from Stevens Institute of Technology and a BSEE from Bombay University.