JESD204B Link Debugging Guidelines
JESD204B provides fewer interconnects which simplifies layout and allows smaller form factor realization without impacting overall system performance. This webcast begins with general JESD204B link debugging guidelines, regardless of product. We then go deeper and provide more details on specific products and platforms, including platforms from Analog Devices, Xilinx, and Altera.
Who Should Attend:
Engineers involved with designing high speed converter applications including: wireless infrastructure (GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA) transceiver architectures, software-defined radios, portable instrumentation, medical ultrasound equipment, Military and Aerospace.
Del Jones, Applications Engineering Manager, Analog Devices
Del Jones is an Applications Engineering Manager in the High Speed Portfolio team at Analog Devices. With over 35 years of experience in electronics, he has worked with FPGA and board design in Telecommunications and ADC, DAC, and high-speed interface applications in the Semiconductor industry. Del earned his BSEE from the University of Texas at Dallas.
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