Industry Leaders Unveil Shared Vision for 20nm
Industry leaders Cadence, TSMC, and ARM outline their vision for 20nm silicon success
If you are designing or planning to design at 20nm process technologies, don’t miss this webinar.
At 20nm, there are multiple new and disruptive design and manufacturing discontinuities that must be understood and handled to ensure successful silicon. Moving to advanced node technology calls for a paradigm shift in the way ICs are designed and manufactured.
In this webinar, ecosystem leaders will walk you through 20nm challenges and offer their experiences, guidance, and recommendations to help you gain clarity on how to succeed at advanced node design.
Attend this webinar to bring your 20nm design to life. Attendees will be entered in a drawing to win an Apple® iPad. Official rules.
Find out what it takes to enable foundry-optimized, higher-performance, lower-power designs at 20nm.
David Desharnais, Group Director, R&D, Silicon Realization Group, Cadence
David serves as the head of Product Management for Silicon Realization Group Research and Development. In this role, he has responsibility for the entire portfolio of digital, analog/full custom, and signoff product lines across design, verification, and implementation flows, targeting high-performance, low-power, mixed-signal, and advanced-node SoCs. Prior to David’s current role, he held various management positions in design, process engineering, field applications, and marketing at companies including Pixelworks, Lattice Semiconductor, and Sharp Microelectronics. David holds a BSEE and MBA from University of Washington and serves on the Sequent Product Management Executive Board.
Tom Quan, Deputy Director of Design Methodology and Service Marketing, TSMC
Tom Quan joined TSMC in 2007 as deputy director of design methodology and service marketing. Current he is the director of Open Innovation Platform® Marketing. Prior to joining TSMC, Tom was vice president of marketing in Applied Wave Research, Inc. and has held several senior management positions at Cadence Design Systems, Inc. Tom began his career at Intel Corporation as an IC designer. Tom has over 25 years of experiences in chip design, technical/product marketing, strategic planning and business development in electronic design software industry. Tom holds an MBA degree from Santa Clara University and a BS degree in Electrical Engineering from University of California, Berkeley.
Senior Principal Engineer, Physical IP Division, ARM
YK serves as
the memory architect for the Physical IP Division. In this role, he has
responsibility for the design of high-performance, high density, and low power
memory architecture. YK holds a BSEE and MSEE from Mississippi State University.
You are also invited to attend the following Cadence webinars. Attendees will be entered in a drawing to win an Apple iPad. Register to attend! http://www.cadence.com/20nm
- May 2 at 9am PT: Cadence and Samsung Present a Digital 20nm Solution
- May 3 at 9am PT: Cadence and IBM Presents a Custom 20nm Solution
Please disable any pop-up blockers for proper viewing of this webinar.