This webinar will be 60 minutes. It is intended for all designers who are either already prototyping their ASIC design or are considering prototyping their next ASIC design. Learn about best practices and new HAPS-70 system technology that will increase the productivity of FPGA-based prototypes for software development, hardware/software integration and system validation.

In this webinar, viewers will learn:

  • Up to 3x improvement in system performance enabled through enhanced HapsTrak 3 I/O connector technology and high-speed time-domain multiplexing (HSTDM)
  • Modular system architecture scales from 12-144M ASIC gates to accommodate a range of design sizes, from individual IP blocks to processor subsystems to complete SoCs
  • New capability in Synopsys’ Certify software in combination with HAPS’ flexible interconnect architecture accelerates multi-FPGA partitioning by up to 10x
  • Enhanced Universal Multi-Resource Bus host connectivity of up to 400 MB/s facilitates debug and increases hybrid prototyping performance with Synopsys’ Virtualizer
  • Pre-validated Synopsys DesignWare IP with HAPS systems enables efficient integration of IP blocks and earlier software development

Neil Songcuan, Senior Product Marketing Manager, Synopsys
Neil Songcuan is a Senior Product Marketing Manager with Synopsys, who is responsible for the FPGA-based Prototyping Solution. His experience includes the areas of semiconductor, hardware-assisted verification and system validation. Neil has held various marketing management positions with Synplicity, Mentor Graphics and IKOS Systems. Additionally, Neil previously held customer marketing and application engineering roles with Altera Corporation. Neil holds a B.S. degree in Electrical Engineering from San Jose State University.