Please join our free 45-minute webinar (including a Q&A) to learn how IC Validator, a new In-Design physical verification solution, can help speed up your tapeout schedule.

Modifying your layout after implementation can affect other design targets such as timing, power and signal integrity. In-Design physical verification provides a push-button flow for signoff quality metal fill and Design Rule Checking (DRC) inside IC Compiler where timing can still be considered. Our physical design and verification technologists will show you how new IC Validator In-Design physical verification combines timing awareness and signoff accuracy to speed up your tapeout schedule.


Kerstin McKay is CAE director for Synopsys’ Physical Verification products and has been with Synopsys since 2002. Kerstin received her Master of Science degree in Physics with Advanced Studies in Biomedical Engineering from the University of North Carolina at Chapel Hill.