Today, more than ever, FPGAs are a platform for developing advanced system-on-a-chip products. Engineers are integrating more functionality then ever before enabled by larger capacity FPGAs that include high-speed serial transceivers, high performance clocking, and signal processing. With this integration comes the desire to leverage available IP for common functions such as memory interfacing, encoding/decoding, processing, and more. The challenge—IP is available from third party providers but without a common interface with devoted resources to link and tie IP together and then verify that it works within the designer’s system.
Now there is a better way. Xilinx has helped to define the AXI4™ interface, a common interconnect that enables customers to easily link and combined IP within an FPGA. Even better news—it’s available now.
This webcast will explain how this new IP interconnect works and how it enables plug-and-play FPGA design to increase your productivity. You will learn how this new interconnect has been defined to address your diverse system requirements such as increased bandwidth, low latency, and resource utilization. You will also learn how Xilinx FPGA design flows—including those for logic, connectivity, embedded, and DSP—have been optimized to use AXI4. Finally learn how standardizing on a common interconnect will increase IP availability within a more robust IP ecosystem.
Attendees will learn:
  • What is AXI4 and how it enables plug-and-play IP design
  • How AXI4 improves productivity
  • How AXI4 interface provides the flexibility to increase system bandwidth and reduce system latency for higher performance systems
  • How AXI4 will promote greater availability through the Xilinx IP Ecosystem
  • How to begin the transition to AXI4 today
Who should attend:
  • FPGA Designers
  • SoC Designers
  • Engineering or Technical managers
  • System Architects
  • ASIC Designers Interested in FPGA design
Craig Abramson, Product Marketing Manager, Xilinx, Inc.
Craig Abramson has been with Xilinx for over 10 years as both a Field Applications Engineer and a Marketing Manager. 
Currently he is a Marketing Manager for the IP and SW organization, supporting the company-wide transition to AXI.  He is also the Product Marketing Manager for the MicroBlaze Soft Embedded Processor. Prior to joining Xilinx he worked as an Embedded Design Engineer on a variety of real-time robotic and imaging systems.