Implementing High-Performance FIR Filters and FFTs in 28-nm FPGAs
Finite impulse response (FIR) and fast Fourier transforms (FFTs) are two of the most common digital signal processing (DSP) functions implemented in FPGAs. In this webcast, you’ll learn how the FPGA industry’s first variable-precision DSP architecture, available in 28-nm Altera® FPGAs, is optimized for FIR and FFT implementation.
Watch this 25-minute webcast to find out how variable-precision DSP block features can:
- Efficiently implement FIR filters by incorporating a built-in pre-adder, co-efficient registers, and two levels of adder tree within the DSP block architecture
- Implement FFTs with only half of the silicon resources required by competing FPGAs by incorporating unique features for complex multiplication across various bit widths
Suhel Dhanani, Sr. Manager, DSP Marketing
Suhel Dhanani is a Senior Manager in the software, embedded and DSP marketing group. Mr. Dhanani is responsible for DSP product marketing. He has over 15 years of industry experience in the semiconductor industry, specializing in digital signal processing. Mr. Dhanani has completed a graduate certificate in Management Science from Stanford University and holds M.S.E.E. and M.B.A. degrees from Arizona State University.
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