Successful low-power IC designs implement several power management schemes through a comprehensive design, implementation and verification tool chain that understands the power intent. These designs include a large portion of embedded memories that dominate the chip’s power allocation. We will present memory techniques that enable chip designers to stay within their power budget.

What you will learn:

  • How to minimize low-power design complexity with IP that is optimized for power, performance and density
  • The trade-offs and practical implementation of various power management features
  • How the DesignWare® IP portfolio of SiWare™ Embedded Memories are suitable for mobile SoC applications

Who should attend: 
Designers that are or will be designing complex SoCs targeted at mobile applications in 40nm or 28nm technology nodes.

Estimated length: 50 minutes, 10 minutes Q&A

Prasad Saggurti, Product Marketing Manager, Synopsys
Prasad Saggurti is the Product Marketing Manager for Embedded Memory and Test & Repair IP at Synopsys. Prior to Synopsys, Prasad held senior engineering and marketing roles at MoSys, ARM, National Semiconductor and Sun Microsystems. Prasad has an MSEE from the University of Wisconsin-Madison and an MBA from the University of California-Berkeley.