How To Pass The Receiver Compliance Test For PCI Express®
This presentation reviews how to approach PCI Express receiver compliance test. We will discuss the different flavors of the PCI Express 2.0 specifications ("base" and "CEM"), clock topologies ("data clocked" and "common reference clock"), and the requirements for receiver test. We will review peculiarities of the PCI Express jitter tolerance specification (frequency response of RJ and residual SSC), the receiver test set-up, test methodologies, and latest measurement solutions from Agilent Technologies.
Duration: One hour
Who Should Attend:
R&D designers, engineers, and project managers working on high-speed digital designs; who spend a significant amount of time in the debug and validation phase dealing with signal integrity related problems in their designs.
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After receiving his Diploma in Electrical Engineering from the Ruhr University of Bochum, Germany, Michael joined HP in 1980 as an R&D engineer for Pulse generator HW designing discrete and integrated output stages. He then became Project leader fo HPs 1st optical average power meter, attenuator and OTDR. Back at HP's line of logic signal sources as an R&D project manager he lead the development of HP's 1st data generator analyzer system for physical layer test, 1st multiple serial BERT and initiated the 1st Parallel BERT as a strategic product planner. His technical work resulted in several patents related to fiber optic components, electronic circuits and measurement methods. For an eight year period he lectured electronics at the Stuttgart "Berufsakademie", a college for Diploma Engineers (BA). Today, besides his strategic planning work he's active in standardization, with contributions within IEEE, OIF and PCI-SIG; momentarily his main technical interest is the field of signal integrity and jitter (tolerance) testing.
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