Application-specific processors (ASIPs) are the solution of choice when design teams determine that standard processors do not meet performance /power requirements, and fixed hardware does not provide enough flexibility. While each ASIP is software-programmable, its architecture is optimized for the set of functions that it has to implement, with some margin for algorithmic evolution. Obviously, architectural exploration is at the heart of an efficient ASIP design flow – getting started quickly with an initial architecture, and then iteratively refining it towards the optimization goal.

Attend this webinar to gain a demonstration of the architectural exploration flow based on IP Designer, Synopsys’ ASIP design tool. Starting from an initial RISC architecture, we will demonstrate how to come to an application specific architecture, featuring instruction-level and data-level parallelism


Werner Geurts
CAE Manager, Synopsys

Werner Geurts is the CAE manager for ASIP design tools at Synopsys. Before joining Synopsys, he co-founded Target Compiler Technologies, a pioneering company providing retargetable tools for the design of application-specific processors. Between 1989 and 1996, Werner was a researcher at IMEC, where he worked on behavioral synthesis of datapath structures and on retargetable compilation. Werner has co-authored several papers on the topic of electronic design automation. He holds master’s degrees in electrical engineering from the Hogeschool Antwerpen and K.U. Leuven, and a Ph.D. from K.U. Leuven.”