How to Enable Prototyping of Multi-Million ASIC Gate Designs
Learn how the new HAPS-600 series of FPGA-based prototyping systems enables early hardware & software validation, debug, and development for much larger SoC projects than ever before. The webinar introduces this new addition to the HAPS family and provides an overview of the complete solution, which includes integrated and scalable hardware plus comprehensive software tool flow. Designers can reduce initial turnaround times and subsequent iterations with the HAPS-600 series’ highly automated software flow from RTL code to the FPGA-based prototype utilizing Synopsys’ patented programmable switch routing technology.
What attendees will learn:
- How to implement a multi-million ASIC gate design into a multi-FPGA-based prototyping system by using a semi-automated flow and flexible hardware interconnect architecture
- How to use co-simulation for quicker system bring-up
- How to debug a design over multiple FPGAs
Michael Posner, Product Manager, FPGA-Based Prototyping Solutions & DesignWare IP for SATA, Synopsys
Michael Posner joined Synopsys in 1994 and is currently a Product Manager for Synopsys’ FPGA-Based Prototyping Solutions & DesignWare IP for SATA. Previously, he has held various application consultant and technical marketing manager positions at Synopsys. He holds a Bachelors Degree in Electronic and Computer Engineering from the University of Brighton, England.
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