How to Create Low-Power FPGA Designs
Power usage is a critical element of system design. Battery-powered, handheld devices, medical systems, and networking applications are the most obvious power-sensitive systems. However, even power-hungry applications like cloud application servers, hardware accelerators, and crypto currency mining, can receive appreciable operating cost savings by reducing power by just a few percentage points.
This webinar focuses on design techniques for saving power, including system level design, RTL architectural decisions, and low-level techniques, as well as the role of process and power-friendly FPGA features.
Attendees will learn:
- Sources of power dissipation
- Optimization techniques for static and dynamic power reduction, including techniques for gating clocks and signals, selecting data path elements for low power, and state machine encoding
- Advanced practices for power-sensitive designs
- The impact of FPGA process technology and architecture on power consumption
- Designing at the system and board level for low power
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