FPGA-based prototypes offer tremendous value for IP block validation and confirming that a SoC design will integrate properly with software because they deliver system performance and real-world I/O connectivity. The combination of high clock speeds and realistic interfacing scenarios makes hardware/software validation feasible months before test silicon is available. But the bring-up effort for an FPGA-based prototype has traditionally been a challenge to complete within the short schedule from when ASIC RTL is first available and tape-out of test silicon. The urgency for prototypes to be up and operational quickly has ushered in a new class of EDA tools to help accelerate design migration and debug of ASIC RTL and IP specifically for FPGA-based prototypes. This webcast examines the latest generation of design tools for prototyping, Synopsys ProtoCompiler, a suite of design automation and debugging tools for the Synopsys HAPS Series of FPGA-based prototypes.

Attendees Will Learn:

  • Typical challenges of FPGA-based prototype bring-up and debug
  • Typical IP block and subsystem validation methods
  • Introduction to the ProtoCompiler design processing workflow and data model
  • Introduction to ProtoCompiler debug and system assembly automation features
  • Benchmark results and case study using ProtoCompiler

Who Should Attend:

  • ASIC/SoC prototyping and emulation specialists
  • ASIC/SoC hardware designers
  • ASIC/SoC verification specialists


Troy Scott
Product Marketing Manager, Synopsys

Troy Scott, a product marketing manager, is responsible for FPGA-based prototyping software tools at Synopsys. He has 20 years of experience in the EDA and semiconductor industries. His background includes HDL synthesis and simulation, SoC prototyping, and IP evaluation and marketing.