Overview:
For FPGA signal processing applications,
mapping to device structures like DSP and memory blocks has long been a
requirement for reaching higher throughputs and overall quality of results
(QoR). However the effort gets very complicated when designs scale to high
multichannel configurations with pipelining, bitwidth growth, flow control, and
use of parallel architectures for common DSP functions. Furthermore, techniques
for achieving QoR usually have a drastically negative effect on design reuse
when re-targeting next-generation devices or different device families. In
summary, a lot of the specialized design and verification effort that goes into
achieving DSP results ends up being repeated for the next project.

This seminar touches on some best practices for creating high-throughput
signal processing designs for FPGAs, with a focus on achieving quality of
results and design reuse across FPGA devices, families, and vendors.
Key topics include:

  • Inferencing of FPGA DSP and memory resources with HDL coding and high-level
    design
  • Managing pipelining and flow control
  • Fixed-point verification for productivity and reuse
  • Parallel architectures for common DSP functions: parallel FFT example
  • Scaling to high multi-channel designs: example 64-channel DDC for MIMO radio
    / phased-array radar

Length: 50min + 10min Q&A

Who should
attend:
DSP/FPGA/ASIC engineers doing IC designs for basestations,
MIMO and software defined radio (SDR), radar, satellite communications,
broadcast and telecom wireless , military radios, and communications IP cores
targeting Xilinx, Altera, Lattice, Microsemi or ASIC.

Presenter:
Chris
Eddington, Senior Technical Marketing Manager, Synopsys

Chris
Eddington is a Senior Technical Marketing Manager at Synopsys and has over 20
years of experience in ASIC and FPGA design. He has held various roles in
technical marketing, algorithm development and IC design at semiconductor
companies that develop video and audio conferencing ICs, high-speed networking,
and wireless communications systems. He holds an MS engineering degree in
digital signal processing from the University of Southern California and an
undergraduate degree in Physics and Math from Principia College.