Tune in to learn how to take advantage of SystemVerilog constructs in Synthesis to boost your productivity. See how the use of SystemVerilog constructs can result in concise, portable RTL that is easier to maintain and consistent with verification needs.

The webinar will show how SystemVerilog constructs such as packages, structures, interfaces and assignment patterns can be easily incorporated in your design. Synopsys’ synthesis experts will share best practices to use these constructs in Design Compiler and provide recommendations to create compact, and reusable RTL for improved productivity.

Participate in live Q&A and get your answers in real time from members of the Synopsys Design Compiler product team. 

Moderator: 
Liz Chambers
, Product Marketing Manager for Design Compiler 

Presenter: 
James Argraves
, Corporate Applications Engineering Manager for HDL Compiler
James Argraves manages the Corporate Application Engineering staff for HDL Compiler at Synopsys. He has over 15 years experience in the EDA and semiconductor industry and has been at Synopsys since 2001. Prior to that he held ASIC design positions at Raytheon Systems and Sun Microsystems. James received a BS in Electrical and Computer Engineering from the University of Illinois at Champaign-Urbana.