Overview:
Traditionally designers use SPICE for accuracy and
FastSPICE for capacity or performance. Parallelization has helped improve
capacity and performance of SPICE. FastSPICE has not improved sufficiently in
accuracy and usability, especially when you consider process variation effects
and for low power designs. This webinar will demonstrate how NanoSpice pushes
Parallel SPICE capacity to greater than 100M element levels and will share
performance benchmarking data. Analog and Memory application cases will be shown
as well as NanoSpice use cases with High Sigma Monte Carlo.

What
attendees will learn:

  • About the evolution of simulator technology over generations in response to
    design trends
  • Simulation speedup benchmarking for challenging and large pre-and
    post-layout memory and analog designs
  • About speedup delivered by tightly integrated simulator and variation
    analysis tools
  • How NanoSpice is used along with IBM-licensed High Sigma Monte Carlo
    solution for yield optimization

Who should
attend:

Engineers and managers designing at deep nanometer
technology nodes or working on complex low power designs.

Attendees will
also have a chance to interact with the presenter during a 10-minute Q&A
session. Attendees can also contact ProPlus (t-support@proplussolution.com)
directly after the Webinar.

Presenter:
Dr.
Bruce McGaughy, Chief Technology Officer & Senior Vice President of
Engineering, ProPlus

Dr. Bruce McGaughy currently serves as the
Chief Technology Officer and Senior Vice President of Engineering of ProPlus
Design Solutions, Inc. He was most recently the Chief Architect of Simulation
Division and Distinguished Engineer at Cadence Design Systems Inc. Dr. McGaughy
previously also served as a R&D VP at BTA Technology Inc. and Celestry
Design Technology Inc., and later an Engineering Group Director at Cadence
Design Systems Inc.

Dr. McGaughy holds a Ph.D. degree in EECS from the
University of California at Berkeley.