To keep pace with next-generation ‘smart devices’, SoC designers require optimal performance, headroom, innovative power management technology and advanced levels of concurrency to match the increased capabilities demanded by consumers. High-performance, simultaneous application processing for smart phones, mobile video and tablets is no longer optional—it’s a must-have for all devices. As designers look at integrating high-frequency on-chip networks onto their SoCs, it is essential for them to have the necessary performance to run multiple, high-speed applications simultaneously to fully leverage the capabilities of their entire system.

In this webinar, Sonics will show SoC designers and system architects how to:

  • Maximize data flow concurrency, minimize power and deliver peak performance levels in any SoC
  • Design an SoC using the highest frequency network-on-chip (NoC) solution at speeds of a GHz and beyond
  • Use intelligent system partitioning to manage complex, multi-function SoCs with multiple clock and power domains
  • Save significant power and cost for even the most complex SoC designs

Frank Ferro, Director of Marketing, Sonics, Inc.
Frank Ferro is the Director of Marketing for Sonics and is responsible for the company’s complete portfolio of on-chip network IP products. Mr. Ferro has more than 25 years of experience in the semiconductor industry and has worked extensively in the communications and consumer electronics fields—with expertise in the areas of WLAN, Voice over IP, cellular phones, personal computers and SoC architectures. Mr. Ferro holds an Executive MBA from the Fuqua School of Business at Duke University and an M.S. in Computer Science, as well as a B.S.E.T. in Electronic Engineering Technology from the New Jersey Institute of Technology.