Get More from the New TSMC 16FFC Process with Optimized Foundation IP
TSMC’s new 16nm FinFET Compact (16FFC) process provides both an easy migration from 28nm processes and additional power and area advantages. To develop the most competitive SoCs in this process, designers should choose optimized foundation IP building blocks (embedded memories and standard cell libraries) for the highest possible performance with lowest power and area. With the combination of the TSMC 16FFC process and the right foundation IP, designers can develop SoCs for applications from high-end green servers and network processors to ultra-low power mobile devices, consumer products, and wearables—and everything in-between.
Attend this webinar to learn about:
- How to take advantage of the new TSMC 16FFC process for your SoC coming from larger technologies or transitioning from the 16FF+ process
- How optimized embedded memories and logic libraries can enable your SoC design to deliver required performance while minimizing area and power
- How combining innovative power management techniques using multiple VTs/channel lengths in different SoC logic blocks and multiple power modes built into embedded memories can deliver the optimal tradeoffs in SoC millwatts per gigahertz
Who should attend?
SoC designers and system/chip architects who are interested in optimized Foundation IP for SoCs coming from larger technologies or transitioning from the 16FF+ process
Ken Brock, Product Marketing Manager, Logic Libraries, Synopsys
Ken Brock is Product Marketing Manager for Logic Libraries at Synopsys and brings 25 years of experience in the field. Prior to Synopsys, Ken held marketing positions at Virage Logic, Simucad, Virtual Silicon, Compass Design Systems and Mentor Graphics. Ken holds a Bachelor’s Degree in Electrical Engineering and an MBA from Fairleigh Dickinson University.
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