Overview:
The webcast covers the fundamentals of clock
synthesis and distribution. It covers the various types of phase-locked loops
(PLLs), the key features of these devices, and which end market they are
designed for. Concepts such as reference switchover, holdover, phase noise,
jitter, output drivers, and signal integrity will be covered.

Who should attend?
Students and engineers new to the
field, as well as those more experienced engineers looking for a refresher on
this or any other part of the signal chain, design, and layout.

Presenter:
Paul Kern, Clock Applications
Engineer, ADI

Paul Kern graduated with a BSEE and MSEE from Santa
Clara University in 1990 and 1992, respectively, with a specialty in microwave
circuits and digital magnetic recording. Mr. Kern has over 5 years experience in
data storage, and over 15 years of experience in applications engineering and
high speed digital circuits. He is currently a Clock Applications Engineer with
the Linear and Radio Frequency Group, located in Greensboro, NC.