In this webinar you will learn how the built-in features of the Lynx Design System can help you achieve predictable design closure with superior results for low power chips. Using real design examples, we will demonstrate several advanced methodologies including multi-corner multi-mode (MCMM) optimization, “what-if” exploration of optimal tool settings and floorplan alternatives, on-demand loading (ODL) for virtual flat design planning, and advanced OCV and distributed multi-scenario analysis (DMSA) for timing signoff . We will also demonstrate in-design physical verification, signoff DRC autofix, and end-to-end hierarchical UPF implementation. Learn how the Lynx Design System can help you leverage the latest EDA tools and methodologies to meet your SoC design objectives in an efficient, predictable manner.

Aditya Ramachandran
Aditya Ramachandran is a CAE for the Lynx Design System. Prior to joining the Lynx team at Synopsys, Aditya had 6 years of experience in ASIC methodology and technology development.

Neel Desai
Neel Desai is the product marketing manager for the Lynx Design System. He has over 14 years of EDA and semiconductor experience spanning both technical and marketing responsibilities. He spent 8 years as the Product Marketing Manager for Design Compiler, Synopsys flagship synthesis product. Neel received his BSEE from University of Bombay, India, his MSEE from Pennsylvania State University and his MBA from Santa Clara University.