Almost every digital SoC, ASIC and ASSP is prototyped in FPGAs; sometimes as a high-performance verification platform, but most often to get a head-start in developing software for the SoC. No matter what the purpose though, it is difficult to do and it takes too much time and too much effort, to get the prototype up and running.

But does it really have to be so hard?

In this seminar we will discuss, combined with a methodology based in best practices, how state-of-the art FPGA devices can change the way we do FPGA-based prototyping, making it easier to use, easier to deploy and much, much faster to get the prototype up and running.

Topics to be covered:

  • The big picture: what is prototyping good for and what it’s not good for
  • Common challenges and issues
  • Making life easier: choosing the right tool for the job
  • The icing on the cake: tips and tricks on how to get the most out of your FPGA-based prototype

Who should attend:

  • verification engineers 
  • system integrators
  • ASIC designers
  • embedded software, firmware, driver, operating system developers

Phil Simpson, Senior Manager for Software Technical Marketing, Product Planning and EDA Relationships, Altera
Phil Simpson is Altera’s senior manager for software technical marketing, product planning and EDA relationships. In this role, he is responsible for Altera’s Quartus II software and third-party EDA interfaces product planning and the creation of the Altera FPGA design flow roadmap. Prior to joining Altera in 1997, Mr. Simpson held several engineering roles at various EDA and semiconductor companies, including EDA Solutions, Data I/O and Graseby Microsystems. He holds a BSc (with honors) in Electrical & Electronic Engineering from City University, London and an MSC (with distinction) in system design from the University of Central England, Birmingham, UK. Mr. Simpson is a published book author on team-based FPGA design. 

Juergen Jaeger, Sr. Product Marketing Manager, Cadence Design Systems
Juergen Jaeger is Sr. Product Marketing Manager at Cadence Design Systems in San Jose, CA. He has over 20 years of experience in hardware and software design and verification in the ASIC and FPGA space. He holds a BSEE degree from the Fachhochschule of Kaiserlautern, Germany and a masters degree in computer science from the University of Hagen, Germany.