Up through 28-nm, planar CMOS processes were the mainstream offering. A few foundries are now offering FinFET processes from 16-nm and 14-nm. For certain applications, FinFET processes offer many attractive features, but moving to FinFET does not make sense for all SoC designers. In this webinar, Synopsys will present reasons why moving to FinFET may or may not be appropriate. Synopsys will also present the portfolio of DesignWare® Logic Libraries and Memory Compilers on FinFET processes that are most appropriate for different target applications.

Attendees Will Learn:

  • The benefits and challenges of moving from a planar process to FinFET
  • Whether a FinFET process is right for your next SoC
  • How an optimized portfolio of embedded memories and logic libraries can enable your FinFET move

Who Should Attend:

SoC design engineers, system architects, project managers


Prasad Saggurti
Product Marketing Manager, Embedded Memory IP, Synopsys

Prasad Saggurti is the Product Marketing Manager for Embedded Memory IP at Synopsys. Prior to Synopsys, Prasad held senior engineering and marketing roles at MoSys, ARM, National Semiconductor and Sun Microsystems. Prasad has an MSEE from the University of Wisconsin-Madison and an MBA from the University of California-Berkeley.