Please join our free 45-minute webinar (plus a Q&A) to learn how you can use in-design rail analysis to accelerate the path to final design closure.

Finding power grid issues in the late stages of physical implementation can lead to painful rip-up and repair iterations. In-design rail analysis with PrimeRail provides a push button flow inside IC Compiler that enables you to analyze and identify potential problems earlier where changes are less intrusive. Join our experts to learn how you can use in-design rail analysis to analyze and debug voltage drop, power up and electromigration (EM) effects as early as placement, accelerating the path to final design closure.

Attendees of the live event who also submit the feedback form will be eligible to win a Free 8GB iPod Touch (value approx. $250) Official Rules


Tom Chau is group CAE director for Synopsys’s power/rail analysis and library characterization products and has been with Synopsys since 1995. Tom has more than 23 years combined semiconductor and EDA industry experience and is responsible for strategic customers’ reference flow development with the focus on low power design. Tom received a B.S. degree in Electrical Engineering from University of California, Berkeley and a MBA from San Jose State University.

Dr. Henry Sheng is R&D Group Director for Design Closure in IC Compiler. Henry and his organization are responsible for implementation extraction, timing and signal integrity, as well as Multi-corner Multi-mode (MCMM) and post-route closure. He has been with Synopsys since 1996. Henry holds a Ph.D. degree in Electrical Engineering and Computer Science from the University of California, Berkeley.

For information on other Synopsys IC Compiler 2009 Webinar Series events click here