Faster Design Closure with Congestion Minimization
Routing congestion can cause painful iterations between synthesis and implementation, reducing your productivity and delaying your design closure. Design Compiler Graphical is the RTL synthesis solution that enables you to predict, visualize and alleviate congestion and ease routing prior to physical implementation. This webinar will show you how predictable routing congestion from synthesis to tapeout eliminates unnecessary iterations, speeding up your overall turnaround time.
Janet Olson is R&D group director for DC-Graphical and DC-Topographical technologies in Design Compiler. Janet and her organization are responsible for the optimization engines within Design Compiler. She has been with Synopsys since 1993. Janet holds a Masters degree in Electrical Engineering from Stanford University.
JC Lin is VP of Engineering at Synopsys. JC has been with Synopsys for more than 15 years working on various technologies, including RTL Synthesis and Physical Synthesis. Currently, JC leads the placement and clock tree synthesis (CTS) teams for IC Compiler. He holds a Ph.D. degree in Computer Science from State University at New York (SUNY) at Stony Brook.
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