Getting to signoff-quality timing constraints is vital to efficient timing closure. 

This technical webinar will explain how Galaxy Constraint Analyzer helps to produce signoff-quality timing constraints quickly, for even the most complex designs. Hear how AMD uses Galaxy Constraint Analyzer for timing constraint quality assurance. Learn about new features to check constraint consistency between chip level and block level including blocks that are instantiated multiple times and how constraint changes throughout the design process can be validated. 

Galaxy Constraint Analyzer ensures the use of clean, consistent constraints across arbitrary levels of hierarchy and validates late arriving constraint changes to maximize the efficiency of the Galaxy Implementation Platform. Its fast runtime speeds timing constraint cleanup on million-instance designs that have hundreds of clocks, dozens of scenarios, multiple levels of hierarchy and rapidly evolving design constraints. 

Who should attend 
Designers & managers responsible for timing constraints, design implementation and signoff. 

Richard Bishop
Member of Technical Staff 

Richard Bishop has 14 years of experience in the areas of Synthesis, Static Timing Analysis, Place & Route, and CAD Flow Development. In his current role as Member of Technical Staff at AMD, he is a Front-End Timing Lead for one of AMD’s next-generation Graphics Processing Units. Richard received his BSEE degree from Washington State University and his MS degree from Wright State University.

Karen Linser 
Senior Corporate Applications Engineer Implementation Group 
Karen Linser is currently a Senior Corporate Applications Engineer at Synopsys supporting Galaxy Constraint Analyzer. After moving from design into EDA in 2001, she has focused on transistor and gate level static timing analysis. Karen received a BS in Electrical Engineering from the Missouri University of Science and Technology.