Fast FPGA Design Debug Using Simulator-like Visibility into FPGA Hardware Operation
The increasing size and complexity of FPGA designs are increasing, driving a need for in-system FPGA debug. The traditional node-based FPGA debug tools are no longer able to achieve the requirements of today’s FPGA designs. Designers are in increasing need of FPGA debug tools that accelerate debug through incremental debug and RTL mapping, with much higher visibility.
This webinar introduces the Identify RTL debugger and its ability to instrument RTL HDL and while still at the RT-Level, debug the implemented FPGA on live, running hardware. Designers are able to designate sample triggers, navigate the design graphically, and mark signals in the RTL to serve as probes. After synthesis, the results are viewed through a number of options: RTL source code, the HDL Analyst RTL View or third-party waveform viewer, which ensures RTL-to-implementation equivalence and correct operation of the FPGA design. FPGA designers will learn how to use Identify RTL debugger to efficiently debug and verify their design in hardware, similar to simulation—only much faster and with in-system stimuli.
Attend this webinar to learn about:
- How and where to instrument
- How to set triggers and breakpoints to pre-instrument a FPGA design
- Techniques to ensure fault capture
- How to use debug data to resolve design faults
Who should attend?
All engineers/managers involved in FPGA designs targeting end market applications in military, aerospace, automotive, industrial, you don’t want to miss this informative webinar.
Joe Mallett, Sr. Manager, Marketing Synopsys
Joe Mallett, Sr. Manager, Product Marketing for FPGA-based synthesis software tools at Synopsys. He has 20 years of experience in design and implementation in the semiconductor and EDA industries. Before joining Synopsys, he was a Sr. Product Marketing Manager at Xilinx Semiconductor where he worked to define and launch FPGA products. His background includes SoC design/prototyping, embedded software, HDL Synthesis, IP, and Product/Segment Marketing. He holds a BSEE from Portland State University.
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