The sensitivity of circuits to parasitics is intensifying at each new generation of process technology. The advanced node system-on-chip (SoC) designers are looking for high accuracy field solver extraction on larger proportions of designs including custom digital or analog/mixed-signal (AMS) blocks. The StarRC Custom Rapid3D technology offers 20x faster 3D field solver extraction and increased capacity to address the emerging accuracy and turn-around time challenges.

This technical webinar will describe the latest advancements in field solver algorithms incorporated inside the Rapid3D technology that enables high performance and silicon accuracy. It will also discuss its advanced multicore solution that offers near-linear performance scalability on today’s mainstream compute resources. Our experts will demonstrate the ease of use of the field solver extraction using the embedded Rapid3D technology and share results from customer applications including standard cell characterization, memory, custom digital and AMS designs.

Who should attend:
Design engineers and managers who would like to know more about high performance 3D extraction to accelerate their SoC custom designs.

Omar Shah, Staff Engineer, CAE / Extraction, Synopsys, Inc.
Omar Shah is a Synopsys staff CAE with more than 10 years of experience in backend, specifically parasitic extraction and post layout verification flows for reliability and circuit simulation. He has a Masters in electrical engineering with degrees from Purdue University and Cal State.