Next-generation SoCs include an increasing amount of analog IP. Typically these devices contain multiple standard interfaces (USB, Ethernet, SATA, DDR, etc.) and need to handle multiple power domains, clock generation (PLL) and signal conversion (ADC, DAC) all on a single chip.

It is becoming challenging to architect verification environments that can accommodate digital and analog verification. In this webinar, we discuss a methodology that provides a solution to help fill this gap and complements traditional digital verification environments. By using this methodology, it’s possible to create reusable mixed-signal verification environments that enable analog assertions, analog verification planning, analog stimulus and analog self-checkers.


Bradley Geden
CustomSim Product Marketing Manager

Bradley is the product marketing manager for Synopsys’ CustomSim unified circuit simulation solution. He has over 15 years experience in the EDA and semiconductor industries. Bradley started his career as an analog/mixed-signal IC design engineer at the SAMES foundry in South Africa and subsequently joined CML Micro in the UK where he was responsible for leading IC design teams delivering products to the wireless and wire-line markets. Over the last 9 years, he has held product marketing and sales positions at Mentor Graphics and Synopsys. He received his bachelor degree in electronic engineering from the University of Pretoria in South Africa.

Fabian Delguste
Principle Corporate Application Engineer

Fabian Delguste is a Principal CAE at Synopsys. He is in charge of deploying verification solutions to key accounts in Europe. He is also involved with definition, architecture and development of verification methodologies such as VMM and UVM as well as the development of Verification IP.