Learn how DC Explorer enables early RTL exploration leading to a better starting point for RTL synthesis and accelerates design implementation. Hear from Matt Baker, synthesis lead for Snapdragon system at Qualcomm, how DC Explorer helps expedite schedules for highly complex multi-million gate designs. See how the team at Qualcomm was able to refine RTL and constraints faster and begin physical implementation much earlier providing more time in the schedule to further improve Quality of Results.

DC Explorer allows you to efficiently perform what-if analyses of various design configurations early in the design cycle and speed up the development of high quality RTL and constraints. You can also generate an early netlist to begin physical exploration in IC Compiler, even before the RTL is complete, speeding up place and route. See how DC Explorer with tolerance to incomplete design data, 5-10X faster runtimes and 10% timing and area correlation to DC Ultra™(Topographical) can help you achieve a faster more convergent design flow.

<!–Who should attend

Technology and process development engineers and managers, process integration engineers and TCAD engineers.–>


<!––>Matt Baker
Staff Engineer

<!––>Sandra Ma
Sr. Director, Corporate Application Engineer

<!––>Liz Chambers
Product Marketing Manager