In traditional, low density FPGAs you would expect to get FPGA fabric, memory blocks, maybe some DSP, IO and possibly some PLLs. If we look at FPGAs in the < 150K gate range, why not expect more out of your FPGA? Look for FPGAs with more resources in low density devices and see what a difference it can make to device footprint, cost, and overall functionality.

Attendees will learn:

  • How to get SerDes functionality in 10K LE devices
  • How to leverage NVM for secure boot of your FPGA or Micro
  • Which devices are ideal or better for CPLD replacement
  • Which solutions provide superior performance for deterministic motor control
  • Why low power devices are critical for thermal imaging
  • How to prevent overbuilding and cloning in your system
  • About Microsemi FPGA & SoC families

Who Should Attend?
Anyone working with FPGAs in the low to mid-range densities that may be interested in getting more out of their FPGA in terms of features and capabilities.


Ted Marena, Director, FPGA and SoC Marketing, Microsemi

Ted Marena is the director of FPGA SoC marketing at Microsemi. He has over 20 years’ experience in FPGAs. He was awarded Innovator of the Year in February 2014 when he worked for Lattice Semiconductor. Marena has defined, created and executed unique marketing platform solutions for vertical markets including consumer, wireless small cells, industrial, cameras, displays and automotive applications. Marena started working as a design engineer, field application engineer and a sales manager before he moved to marketing. His understanding of the complete electronics design cycle has earned him a reputation as an expert marketer in the semiconductor industry.