ESD Design for High Speed Interfaces: Signal Integrity Considerations (Part 2)
Next generation interfaces such as HDMI 1.4, USB 3.0, eSATA, and DisplayPort present serious challenges to system designers trying to provide adequate protection against ESD threats. In the earlier Part 1 of this series, we focused on techniques for ensuring adequate levels of protection for these high speed interfaces. In Part 2, we turn our attention to maintaining signal integrity when placing ESD devices on high speed differential signals.
Examples of topics covered in this session include:
- Capacitance, inductance, and methods for impedance matching
- Maintaining eye openings, minimizing jitter and skew
- Looking beyond the specifications – comparing signal integrity challenges with different ESD solutions
Jeff Dunnihoo works as a Senior Product Line Applications Engineer with NXP, and is based in Austin Texas. He has extensive experience in the design and application of ICs and systems in the consumer, computer, and telecommunications industry. Jeff is a contributing member of the ESD Association, and has been awarded several patents. Prior to NXP, Jeff worked at California Micro Devices, IBM, SMSC, and Pragma Design. He received his BSEE from the University of Texas at Austin.
Joe Salvador is the Marketing Director for NXP's Integrated Discrete Computing and Consumer business. He has been involved extensively in ESD protection circuits as well as broad experience in semiconductor products and markets. Before joining NXP, Joe held various management and marketing roles at companies such as California Micro Devices and National Semiconductor. He received his Bachelor of Science in Engineering from the University of Pennsylvania and his Masters of Business Administration (MBA) from Carnegie Mellon University.
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