Ensuring Interoperability And Performance Of Your DDR Memory Subsystem
Deciding which variant of DDR memory to use in your design is a balance of speed, power consumption, complexity and cost. Many designers are facing the migration from DDR1 to DDR2, DDR2 to DDR3, or DDR to LPDDR. In each situation, the key challenges are in probing, parametric and protocol characterization, and guaranteeing interoperability. Are you are able to make repeatable, accurate measurements? Will your design survive a change in DRAM vendor? This presentation will review the latest DDR trends, tips for ensuring interoperability, and the latest measurement techniques for characterizing and validating your memory design.
Duration: One hour
Who Should Attend:
R&D designers, engineers, and project managers working on high-speed digital designs; who spend a significant amount of time in the debug and validation phase dealing with signal integrity related problems in their designs.
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|Perry Keller is a Senior Engineer and Program Manager for support of memory design. He has over 23 years of experience at Agilent Technologies in the areas of software and system engineering and high-speed hardware and ASIC design and validation, software engineering, product marketing, and project management. Perry graduated in 1980 from Rice University with a Masters Degree in Electrical Engineering.|
|Ai-Lee Kuan joined Agilent in 2001 and held various positions in manufacturing as a test and product engineer. Her expertise is in high speed bus application with the logic analyzer. She joined the logic and protocol test marketing team in 2007, focusing on the memory market. Ai-Lee holds a Bachelor's degree in electrical and electronics from University of Science Malaysia.|
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