Enhance Designer Productivity with NanoTime’s Graphical Setup and Debug Features
NanoTime is the next-generation transistor-level static timing analysis solution that addresses the challenge of signal integrity (SI) analysis with custom designs. The advanced features in NanoTime enable designers to accurately and quickly identify timing issues early in the design cycle to avoid expensive silicon re-spins. Its seamless integration with Custom Designer provide users with additional productivity improvement such as configuration setup, timing reports with cross probing between schematic and layout and library model generation all within the Custom Designer environment
Kenneth Hsieh, Moderator
Sr. CAE Manager
Darryl Eng is a Sr. Corporate Applications Engineer (CAE) Manager for transistor-level STA supporting NanoTime at Synopsys. Darryl started his electronics career in 1977 at Signetics which was part of Philips where he worked on designing microprocessors. Later he joined Atari for designing circuits for home electronics of game players and computers. In 1985, Darryl went into the EDA working in the area of physical layout and symbolic compaction. He joined EPIC in 1994 supporting power, reliability and layout extraction tools, and later managed the corporate application engineering groups for extraction and reliability. In later half of 2005, he started to manage the CAE team for the NanoTime product. Darryl received a BS in Electrical Engineering from University of California at Berkeley.
Les Spruiell is a member of the Custom Design marketing group at Synopsys, inc. Les’s experience includes 30 years developing, marketing and supporting EDA tools a variety of roles at variety of companies. Most recently Les was director of corporate applications at Xoomsys, a member of the Virtuoso Platform marketing team at Cadence and co-found and vice-president marketing at Antrim Design Systems.
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