Clock jitter is probably the most obscure specification in data converters. Clock jitter creates uncertainty around the moment when an analog-to-digital converter (ADC) samples the signal. It also adds to conversion noise, and the combination reduces overall system performance. As data converters have evolved to ever-higher sampling frequencies and higher resolutions, they become more sensitive to external conditions, including clock timing quality. Therefore, clocks must be treated as delicate analog signals requiring minimal disturbances. This webinar will focus on:

  • Analyzing the effect of jitter on the data converters’ sampling error using the frequency domain and the corresponding phase noise representation of jitter
  • Analyzing the jitter characteristics of oscillators and phase locked loops (PLLs), which are the most common clock sources in the system
  • Reviewing wireless communications application examples to illustrate the sampling error mechanisms and their impact on the performance of the ADCs
  • Presenting typical jitter self-referenced measurements and analyzing their relationships to jitter

Understanding frequency domain mechanisms that relate jitter to sampling errors enables designers to handle the design trade-offs and to achieve optimal system and data converter performance.

Estimated Length: 50 minutes + 10 minutes of Q&A

Who should attend: SoC Design Engineers, Managers and System Architects

Carlos Azeredo-Leme, Senior Staff Engineer, DesignWare Analog IP, Synopsys
Carlos Azeredo-Leme is a senior staff engineer for the DesignWare Analog IP at Synopsys since 2009. Prior to joining Synopsys, he was co-founder and member of the Board of Directors of Chipidea Microelectronics in 1993, where he held the position of Chief Technical Officer. There, he was responsible for complete mixed-signal solutions, analog front-ends and RF. He worked in the areas of audio, power management, cellular and wireless communications and RF transceivers. Since 1994 he holds a position as Teacher at the Technical University of Lisbon (UTL-IST) in Portugal. His research interests are in analog and mixed-signal design, focusing on low-power and low-voltage. Carlos holds an MSEE from Technical University of Lisbon (UTL-IST) in Portugal and a Ph.D. from ETH-Zurich in Switzerland.