Overview:

PCI Express® has increased the chip-to-chip bandwidth possible for PCI based systems. With PCI Express v2.0, also commonly referred to as Gen2, becoming mainstream this year these bandwidth intensive applications can be tackled with Xilinx Virtex-6 Integrated Blocks for PCI Express. Xilinx second generation of integrated blocks builds on the experience from Virtex-5 to deliver the most robust and extremely high-performance PCI Express interface.

Regardless of system bandwidth requirements however, to take advantage of PCI Express links and make them efficient, a Direct Memory Access engine (DMA) is required to move data to and from the FPGA to a processor or another PCI Express device. Working with ecosystem Alliance Partners including Northwest Logic, Xilinx offers the key components to take advantage of the integrated block for PCI Express.

Webcast Attendees Will Learn:

  • The latest advances in PCI Express technology in Virtex-6 and Spartan-6 FPGAs
  • How a Direct Memory Access (DMA) engine can improve system performance
  • How to address complex system requirements with sophisticated tools, IP and the programmable flexibility of Targeted Design Platforms
  • Who Should Attend:

  • HW/FPGA designers
  • System Architects
  • Systems designers
  • Embedded systems designers
  • Presenter:
    Alex Goldhammer, Strategic Marketing Manager, Xilinx Inc.

    Alex is the Strategic Marketing Manager responsible for the PCI Express and Aurora serial connectivity standards at Xilinx. Alex focuses on delivering and enabling all of the components related to as well as planning future roadmaps for these IP.
    Prior to joining Xilinx, Alex held various positions in product management and applications engineering with Integrated Device Technology (IDT) where he defined PCI Express switching products and telecommunications products and supported strategic customers in the networking, communications, mobile, storage and server markets.

    Alex is an active member in trade associations such as PCI Express and closely follows emerging standards.
    He holds a B.S. in Computer Engineering from the University of California, Santa Cruz with an emphasis in system design.