Overview:
PCI Express 3.0 increased the supported data rate to 8
Gbps, which effectively doubles the data rate supported by PCI Express 2.0.
While the data rate was increased, no improvement was made to the channels. As
such, an 8 Gbps channel in PCIe 3.0 experiences significantly more loss than one
implemented in PCIe 2.0. To compensate for this increased loss, PCI Express 3.0
specifies enhanced equalization in the PHY with improved TX equalization,
improved RX equalization, and equalization training.

It is critical that
designers who plan to implement PCIe 3.0 understand these equalization changes
and their impacts. After attending this webinar, registrants will
understand:

  • Why improved levels of equalization are necessary at higher data rates
  • Types of equalization enhancements required for optimal performance at 8
    Gbps
  • The difference between decision feedback equalization (DFE) and continuous
    time linear equalization (CTLE)
  • The need for equalization training and adaptability in PCIe 3.0
  • The importance of proven interoperability between the PHY and the controller

Who should attend: SoC designers and system architects

Duration: 60 minutes

Presenters:
Rita
Horner, Senior Technical Marketing Manager for Analog/Mixed Signal IP,
Synopsys

Rita Horner has more than 20 years’ experience in
mixed-signal circuit design, interconnect, test, and packaging of high-speed
integrated circuits for consumer, computing, and high-end networking ASSP and
ASIC products. As a technical and product marketing manager, she has experience
in ASSP, ASIC and Fiber Optic products, focusing on High Speed Serial
Interconnect. She participated and presented in multiple standards bodies
including ANSI T11, IEEE 802.3, OIF, and SFF Multi Sourcing Agreements.

David
Rennie, Senior Analog Design Engineer for Mixed-Signal Interface IP,
Synopsys

David Rennie is a Senior Analog Design Engineer for
Synopsys’ Mixed-Signal IP, developing next-generation high-speed PCIe and
Ethernet SerDes technologies. David has authored and co-authored fifteen IEEE
conference and journal papers and holds five granted and three pending patents.
He has presented at several industry and IEEE conferences, and is an active
member in the IEEE.