Overview:
Today’s multi-mode, multi-application systems place demanding performance requirements on the global resources of the SoC. Estimating bandwidth with spreadsheets is not viable, when dynamic workloads make it impossible to predict performance across all configurations of the interconnect and memory subsystem. Real simulation and performance measurement are needed to optimize results and avoid over-design. In this presentation CoWare ESL 2.0 solutions are used to generate transaction traffic and optimize interconnect and memory subsystem performance with accurate and measurable results.


What you will learn:

  • Today’s Reality
    • Highest causes of schedule delays
    • The breakdown of traditional RTL methods
    • The limitations of static performance analysis with spreadsheets
      • Multiple initiators
      • Dynamic workloads
      • Complex arbitration schemes
      • QoS capabilities
  • Traffic Generation and ESL Performance Analysis for Interconnect and Memory Subsystem Performance Optimization
    • ESL design tasks
      • Project definition
      • Capturing traffic information
      • Component and platform model creation
      • Performance analysis and optimization
    • ESL solution components
      • Realistic traffic generation
      • Cycle-accurate interconnect and memory subsystem models
      • Reuse of RTL memory controllers
      • SystemC platform simulation and analysis environment
  • Case Study: Multi-Media Sub-System of GSM Chip
    • Design challenges
    • ESL performance analysis and optimization results
    • Project benefits


Duration: 60 minutes


Presenter:
Tim Kogel received his diploma and PhD degree in electrical engineering with honors from Aachen University of Technology (RWTH), Aachen, Germany, in 1999 and 2005 respectively. He has authored a book and numerous technical and scientific publications on electronic system-level design of multi-processor system-on-chip platforms. Today, he is working as a Principal Solution Specialist at CoWare Inc. In this position, he is responsible for the product definition and future direction of CoWare’s SystemC-based Platform Architect product line.