Designing High-Performance TCP/IP Off-load and Protocol Bridging Applications with Virtex-5 FXT and TXT FPGAs
Architecting high performance design means designing with high speed serial protocols, arbitrating across multiple data streams, transferring data to and from the local memory to the system memory and bridging multiple protocols. FPGA based designs, in addition to standard bridging function, also provide capabilities to design multiple offload functions – TCP/IP offload, security processing, hardware acceleration, etc.
FPGA design of these architectures requires the designer to understand and evaluate silicon capabilities, make tradeoffs between system performance, size and design cycle schedules, and also futureproof the application by adopting the right protocols and use-models.
This technical presentation will help designers to understand the basics of FPGA-based high performance designs. It will primarily focus on FPGA implementation of efficient scalable architecture to perform 10G TCP/IP offload on ingress data through a XAUI interface. The design also covers fundamentals of a DMA engine to egress the data through a PCIe interface into the system memory for further processing by microprocessors. System design fundamentals on understanding tradeoffs, performance bottlnecks, hardware vs. software offloads, maintaining efficient data flow, scaling the architecture for the future, etc. will also be addressed.
Finally, a complete demonstration illustrating – a PCIe-10GDMA-XGEMAC-XAUI reference design targeted to a V5FXT board, software drivers and an application running on a linux OS will help the attendees understand the benefits of such implementation on Xilinx FPGA.
Webcast Attendees Will Learn:
Who Should Attend
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