Overview:
Increases in IC speed, faster data transmission
rates, smaller geometries, and an emphasis on low power and longer battery life
has brought power integrity to the forefront of PCB design challenges engineers
face today. To address these power issues, designers need advanced power
integrity tools that allow them to see the complete picture and achieve
signoff-level verification through their analysis.

Attendees will learn
how to perform a comprehensive sign-off quality power integrity analysis
covering both DC and AC power. Common power challenges will be identified along
with discussion of potential solutions. Power analysis concepts will be
re-enforced through real world examples demonstrated using a comprehensive power
simulation and optimization solution that can be integrated into any PCB CAD
environment, including Cadence, Mentor, Altium, and Zuken.

Estimated Length: 1 hour

Who Should Attend?

  • Signal Integrity Engineers
  • Design Engineers
  • Hardware Engineers
  • PCB Designers
  • Engineering Managers

Prerequisites: Basic understanding of PCB design flow

Attendees will learn how to do the following:

  • Locate current hotspots that can lead to reliability
    problems
  • Find the one via among thousands that will fail under stress
  • Identify the impact of interrelated voltage and temperature
  • Generate comprehensive design analysis reports in seconds
  • Eliminate decoupling capacitor over-design to cut costs
  • Recapture design area by eliminating unnecessary decoupling capacitors

Presenter:
Matthew
Harms, Field Applications Engineer, EMA

Matthew Harms is a graduate
of the University of Saskatchewan (Canada) with a degree in Electrical
Engineering. Matthew has worked as a Field Applications Engineer for 12 years
with the last 10 being at EMA where he is focused on simulation, part management
and signal integrity issues.