Reliability is a critical performance factor for semiconductor technologies. Understanding the physics behind wear-out mechanisms provides a technical base for modeling and predicting reliability at the component and circuit levels.

This webinar describes the physical phenomena that can lead to device degradation during circuit operation, and deduces reliability models for CMOS technologies. These models can be used for design optimization (“Design for Reliability”) to enable very robust products, and for reliability risk assessment for advanced operating conditions such as high temperature and high voltage.

The webinar covers the most relevant failure mechanisms in CMOS technologies and suggests practical design techniques to enable: 

  • reliability risk assessments based on aging models; and
  • a sufficient robustness margin per design optimization.

The presented concepts apply to multiple analog/mixed-signal processes.

Markus Ackermann, Engineer Device Reliability

Markus Ackermann is responsible for the development of wafer level reliability test concepts and for reliability characterization of primitive devices in X-FAB’s technology feature sizes from 0.13 µm to 1.0 µm. The main focus of his work is the investigation and modelling of transistor aging, especially in terms of special device approaches (e.g. HV MOS transistors). Markus holds a diploma degree in Physics from the University of Jena, Germany.