JEDEC took seven years to develop the recently
published DDR4 standard. DDR4 is significantly different from DDR3 and
represents the most complex DRAM transition since asynchronous DRAMs made way
for the original SDRAM back in the mid-1990s. SoC designers need to learn about
the subtleties of DDR4 SDRAM to ensure that their designs fully benefit from
DDR4 SDRAM standard’s lower system power and higher overall bandwidth.

This webinar will outline and discuss the major features of the DDR4
SDRAM as they apply to embedded applications and areas that SoC designers need
to give special attention to design their systems to take advantage of DDR4’s

What attendees will learn:

  • The major features of DDR4 compared to DDR3
  • Why the JEDEC standard includes each of the DDR4 features
  • Areas to focus on for the SoC DDR4 memory controller and PHY to maximize
    DDR4 performance
  • Recommendations for successfully implementing DDR4 interfaces

Estimated Length: 50 minutes, 10 minutes Q&A

Who should attend:
This webinar is targeted at
system architects, mobile device and consumer electronics product managers and
designers, design engineers, SoC architects, and project

Allan, Senior Product Marketing Manager for Memory Interface

Graham Allan, Senior Product Marketing Manager for Memory
Interface IP, joined the Solutions Group at Synopsys in June 2007. A veteran of
DRAM and memory design, Graham holds over 15 patents, has spoken at several
industry conferences, and has contributed to the SDRAM and DDR standards at
JEDEC since 1992, including holding a chairmanship position from 1996 to 1999.