DDR SDRAM interfaces have become increasingly difficult to design with their parallel interfaces experiencing data rate increases of an average of 30% per year. This webinar highlights the low power benefits to the overall system when a DDR interface is optimally designed and implemented in embedded applications such as SoCs. It will explore many of the issues encountered when using JEDEC standard DDR memories outside the PC environment for which they were designed and conclude with an overview of the distinct DesignWare DDR IP solutions.

This webinar will outline critical areas to consider for the lowest power DDR interface including:

  • Where power is consumed in embedded DDR systems
  • DDR3 vs. DDR2 power
  • Correcting the "JEDEC-ophile" DDR misconceptions
    • PCs use DIMMs, SoCs use components (and sometimes DIMMs)
  • Selecting the optimal driver and ODT impedances for your system
    • For Writes
    • For Reads
  • Other power related issues
  • Synopsys DesignWare® IP for DDR3/2
    • PHYs
    • Controllers

Estimated Length: 1 hour

Who should attend: SoC design engineers, managers and architects; and PCB designers.

Clive "Max" Maxfield has now spent over a quarter of a century in the electronic, computing, and EDA arenas. In 1980, after obtaining his BSc in Control Engineering (an interesting mixture of math, electronics, mechanics, and hydraulics and fluids), Max joined a design team at International Computers Limited (ICL) creating CPUs for mainframe computers. In addition to designing ASICs and circuit boards, Max has written numerous test programs for functional and in-circuit testers. In the area of digital logic simulation, Max has created models of everything from ASIC cell libraries to microprocessors. Due to his digital expertise, Max was once appointed analog marketing manager at a large EDA company (the world is a funny old place sometimes).

In the early 1990s, Max thought it would be fun to see a book he'd written on the shelves in his local book store, so he penned his first tome Bebop to the Boolean Boogie (An Unconventional Guide to Electronics). Since that time, Max has authored and co-authored a number of books, including EDA: Where Electronics Begins, The Design Warrior's Guide to FPGAs, and How Computers Do Math (Featuring the Virtual DIY Calculator).

Graham Allan, Senior Product Marketing Manager for Memory Interface IP, joined the Solutions Group at Synopsys in June 2007. A veteran of DRAM and memory design, Graham holds 15 patents, has spoken at several industry conferences, and has contributed to the SDRAM, DDR, DDR2 & DDR3 standards at JEDEC since 1992, including holding a chairmanship position from 1996 to 1999.