Debugging and Verifying DDR & DDR2 Memory for Reliable System Operation
Discover how to tackle the issues involved in reliable memory system design in this webinar. Find out how DDR2 SDRAMs, the next generation of memories that will be used in future embedded designs, will be implemented using fast edges, high clock frequencies and low voltages, requiring careful verification and testing to ensure reliable memory system operation. You will learn effective ways to validate and debug your DDR and DDR2 memory in embedded systems designs.
Duration: 20 minutes
David Haworth is a logic-analyzer memory application specialist at Tektronix. He was one of the founders of the VXIplug&play Systems Alliance and SCPI Consortium.
Please disable any pop-up blockers for proper viewing of this webinar.